You are comparing Oranges with Apples again. P100 is a complete different design to KNL you don’t know anything about how much die area is used for what purposes.

You would have to do the exact design to compare two fab processes which is already nearly impossible as everybody in the industry knows if you switch from one fab to another you have to use different tools and there are different design restrictions.

I would say ASML knows a lot more than you people who claim to know things at least they are in the business of semi conductor manufacturing and what exactly are your credentials?

If that’s a custom ARMv8A running micro-architecture based Qualcomm chip that is engineered to run the ARMv8A ISA then windows 10/legacy bloat is currently only optimized to run on that exact custom Qualcomm SKU! And What are the exact differences between the Qualcomm ARMv8A ISA running custom micro-architecture and ARM Holdings reference ARMv8A running reference micro-architectures.

If the Qualcomm chip’s underlying hardware has a larger reorder buffer and a slightly different cache subsystem and such other internal differences then Qualcomm will have had to supply Microsoft’s software engineers with that exact chip’s optimization manuals so that they can produce an optimizing compiler/s that takes into account the Qualcomm CPU’s exact internal idiosyncratic execution and decoding engine differences and other internal CPU hardware subsystems differences.

Intel’s brand of x86 32/64 bit ISA running hardware is different at the micro-code and caching, decoding levels in Intel’s hardware that executes the x86 32/64 bit ISA than AMD’s respective x86 32/64 bit ISA running hardware under AMD’s respective underlying hardware features. So Intel’s assembly language optimization manuals are going to be different than AMD’s assembly language optimization manuals. And the Compiler System Software engineers will have to have the respective CPU makers’ optimization manuals to tune the compiler’s optimization passes to produce compiled code that does not produce excessive cache thrashing or other ill effects in the underlying hardware of any custom CPU micro-architecture that is engineered to run the x86 32/64 bit ISA. The same is true for any custom ARMv8A running micro-architectures.

It’s entirely possible to run one makers x86 ISA based compiled code on another maker’s processor that is engineered to run the same x86 ISA, but that code will not run in an optimized state. Ditto for any custom ARMv8A ISA running custom micro-architectures from those top tier ARM holdings architectural licensees who only license the ARMv8A ISA from ARM Holdings. These top tier architectural licensees engineer their own custom micro-architectures that can execute the ARMv8A ISA! So each of their custom ARM CPU cores requires its own optimization manuals and Optimizing compilers that are tuned to produce optimized code for an exact make/model of custom CPU core.

Anyone using any of Arm Holding’s reference design cores can get buy with the optimization manuals from ARM holdings if they are using any of those exact reference design cores, but for any of the custom ARM cores that have different hardware execution engines that’s going to require some time to optimize for.

It looks like there is also some software translation layers between any CISC x86 based win32 code and the RISC ARMv8A ISA running Qualcomm SKUs, so that’s a whole other bog to wade through!

Your first post was still of good quality (“Guys, guys you can’t just simply compare different Foundry nodes as there is a lot of misinformation and marketing nonsense involved.”), but then you link to a site that itself publishes loads of misinformation and marketing nonsense.

Your post does not qualify as proof in any scientific sense.

Agree this could spell really bad news for Power and AMD, as they will be caught between a rock and a hard place.

PDK’s are not publicly available, you have to get them yourself. I hope we will see more on this topic after more of Intel’s PDK’s become publicly available (which will happen if they did not lied that they are now foundry for LG).

For now, you can look at existing silicon. P100 has 15B transistors (6 TFlops). Intel’s equvalent to this, KNL, is supposed to have twice the transistors count (30B) and consequent double performance. But it only has half of the transistor count (slightly more than half thanks to bigger die area).

Or you can compare processors (SPARC M7). Or you should wait for 14nm ZEN/POWER 9.

Probably someone lied again.

I know this is not exact measurement, but when you look at specific rules (or power limitations for example) at PDK then it became clear.

Yada yada witeken, you are well known Intel TROLL and what Intel wrote is bible for you, even when TSMC publicly said something different. So there is no point to discuss with you.

Do you have any proof to back any of your outrageous claims?

As I do:

https://www.semiwiki.com/forum/content/6160-2016-leading-edge-semiconductor-landscape.html

With AMD Zen coming as well, things are going to get rough for Intel very soon. However, I fear AMD may not be able to win back a whole lot of market share from Intel, because by the time that happens, ARM chips will have taken a significant portion of the market.

But this could mean that perhaps in a few years, Qualcomm will be rich enough from its newly found PC and data center revenues to buy AMD. Then the will will REALLY begin, with Qualcomm going 1 on 1 against Intel in PCs, servers, machine learning, and even super computers. I can’t wait. That sort of competition will help accelerate progress in a lot of areas.